Switching Activity in Bit-Serial Constant-Coefficient Serial/Parallel Multipliers
نویسندگان
چکیده
Bit-serial architectures have the advantage of high throughput, area efficient multipliers. These multipliers are implemented using shift-add operations [1], with full adders and D flip-flops as building blocks. Multiplication with a constant fixed-point coefficient is commonly used in digital signal processing (DSP) circuits, such as digital filters [2][3]. The design of a constant-coefficient serial/parallel multiplier [4], as shown in Fig. 1, is based on shifted sums of the input data. The number of adders (stages) required to implement a multiplier is the same as the number of nonzero bits in the coefficient minus one. A widely-used method to implement the multipliers is based on the canonic signed digit (CSD) representation [5]. If CSD representation is used a minimum number of adders is obtained.
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